This relates generally to filtering circuitry, and more particularly, to dynamically adjustable decimation filter circuitry.
A typical communications link includes a transmitter, a receiver, and a channel that connects the transmitter to the receiver. The transmitter in one integrated circuit transmits a serial data bit stream to the receiver in another integrated circuit via the channel. Typical high-speed transmit data rates are 1 Gbps (gigabits per second) to 10 Gbps. Communications links operating at such high data rates are often referred to as high-speed serial links or high-speed input-output links.
In practice, a system that receives a data stream performs different applications using the data stream that typically require different sample rates of the data stream in real time. Such systems that receive data streams often include decimation filter circuits to filter the received data streams by reducing the sample rate of the data stream to a desired level suitable for a particular application.
Conventional decimation filters perform decimation filtering on received data streams using a number of asymmetric filter coefficients. The asymmetric filter coefficients are convolved with the received data stream by performing a number of multiply operations and addition operations on the data stream and asymmetric filter coefficients in real time. Performing the multiply operations using asymmetric filter coefficients typically requires an excessive number of multiplier circuits on the system, which can occupy valuable chip area and consume excessive system resources.